# Board Channel NumBins BinOrOffset ADCBinLimit0 ADCBinLimit1 ... # Board Channel NumBins BinOrOffset TACOffsetBin0 TACOffsetBin1 ... # Board is 0xYY where YY is top two hex digits of board address # Channel is 0-31; only TAC channels are valid (4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31) # BinOrOffset = 0 for a Bin Limit row, 1 for an Offset row # NumBins must be exactly equal to the number of ADC Bins implemented in the QT VHDL # All ADC Bin Limits must be defined # Each ADC Bin Limit must be equal to or greater than the previous bin limit # An ADC value is in bin 'N' if BinLimit[N-1] < ADC <= BinLimit[N] # The first bin has an implied lower limit of '0' # An ADC value of '0' falls into the first bin # Unused ADC bins should have a limit of 4095 and be the highest ADC bins # At least one bin limit should be 4095 (full range covered) # Slew Corrections come after the QT LUT (ie after TAC Offset/ADC Pedestal Subtraction) # Slew Corrections come before QT Channel Masks #VP001 East 0x16 4 8 0 30 60 95 135 200 300 600 4095 0x16 4 8 1 120 69 38 19 4 -11 -29 -52 0x16 5 8 0 30 60 95 135 200 300 600 4095 0x16 5 8 1 113 65 34 15 0 -14 -32 -56 0x16 6 8 0 30 60 95 135 200 300 600 4095 0x16 6 8 1 117 69 35 17 1 -14 -31 -55 0x16 7 8 0 30 60 95 135 200 300 600 4095 0x16 7 8 1 117 67 35 17 2 -13 -30 -53 0x16 12 8 0 30 60 95 135 200 300 600 4095 0x16 12 8 1 147 96 59 37 19 2 -17 -41 0x16 13 8 0 30 60 95 135 200 300 600 4095 0x16 13 8 1 138 94 60 40 24 9 -9 -32 0x16 14 8 0 30 60 95 135 200 300 600 4095 0x16 14 8 1 139 90 55 34 18 1 -18 -43 0x16 15 8 0 30 60 95 135 200 300 600 4095 0x16 15 8 1 132 86 52 32 16 0 -18 -41 0x16 20 8 0 30 60 95 135 200 300 600 4095 0x16 20 8 1 122 73 39 21 6 -8 -25 -49 0x16 21 8 0 30 60 95 135 200 300 600 4095 0x16 21 8 1 123 75 41 22 7 -7 -23 -47 0x16 22 8 0 30 60 95 135 200 300 600 4095 0x16 22 8 1 124 76 41 21 6 -9 -26 -50 0x16 23 8 0 30 60 95 135 200 300 600 4095 0x16 23 8 1 131 80 48 29 13 -1 -19 -43 0x16 28 8 0 30 60 95 135 200 300 600 4095 0x16 28 8 1 112 63 30 13 -2 -16 -33 -54 0x16 29 8 0 30 60 95 135 200 300 600 4095 0x16 29 8 1 120 67 34 16 0 -13 -30 -51 0x16 30 8 0 30 60 95 135 200 300 600 4095 0x16 30 8 1 -10 -13 -13 -15 -16 -19 -24 -35 0x16 31 8 0 30 60 95 135 200 300 600 4095 0x16 31 8 1 115 63 32 14 0 -14 -31 -54 #VP002 West 0x18 4 8 0 30 60 95 135 200 300 600 4095 0x18 4 8 1 111 56 25 10 -11 -21 -38 -63 0x18 5 8 0 30 60 95 135 200 300 600 4095 0x18 5 8 1 98 44 17 -3 -18 -30 -45 -73 0x18 6 8 0 30 60 95 135 200 300 600 4095 0x18 6 8 1 96 50 18 -2 -17 -30 -45 -74 0x18 7 8 0 30 60 95 135 200 300 600 4095 0x18 7 8 1 121 68 33 11 -4 -19 -40 -69 0x18 12 8 0 30 60 95 135 200 300 600 4095 0x18 12 8 1 95 43 12 -6 -22 -33 -49 -74 0x18 13 8 0 30 60 95 135 200 300 600 4095 0x18 13 8 1 97 47 16 -4 -17 -31 -49 -79 0x18 14 8 0 30 60 95 135 200 300 600 4095 0x18 14 8 1 104 57 21 0 -16 -33 -50 -79 0x18 15 8 0 30 60 95 135 200 300 600 4095 0x18 15 8 1 93 45 13 -6 -22 -35 -54 -81 0x18 20 8 0 30 60 95 135 200 300 600 4095 0x18 20 8 1 85 33 4 -15 -35 -46 -63 -89 0x18 21 8 0 30 60 95 135 200 300 600 4095 0x18 21 8 1 82 35 5 -12 -27 -37 -55 -77 0x18 22 8 0 30 60 95 135 200 300 600 4095 0x18 22 8 1 89 41 12 -7 -24 -34 -51 -78 0x18 23 8 0 30 60 95 135 200 300 600 4095 0x18 23 8 1 112 56 23 1 -13 -29 -46 -76 0x18 28 8 0 30 60 95 135 200 300 600 4095 0x18 28 8 1 73 31 4 -8 -16 -28 -40 -60 0x18 29 8 0 30 60 95 135 200 300 600 4095 0x18 29 8 1 76 24 -2 -19 -36 -48 -63 -85 0x18 30 8 0 30 60 95 135 200 300 600 4095 0x18 30 8 1 82 33 3 -18 -32 -43 -61 -87 0x18 31 8 0 30 60 95 135 200 300 600 4095 0x18 31 8 1 87 33 1 -20 -35 -49 -67 -90