# Board Channel NumBins BinOrOffset ADCBinLimit0 ADCBinLimit1 ... # Board Channel NumBins BinOrOffset TACOffsetBin0 TACOffsetBin1 ... # Board is 0xYY where YY is top two hex digits of board address # Channel is 0-31; only TAC channels are valid (4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31) # BinOrOffset = 0 for a Bin Limit row, 1 for an Offset row # NumBins must be exactly equal to the number of ADC Bins implemented in the QT VHDL # All ADC Bin Limits must be defined # Each ADC Bin Limit must be equal to or greater than the previous bin limit # An ADC value is in bin 'N' if BinLimit[N-1] < ADC <= BinLimit[N] # The first bin has an implied lower limit of '0' # An ADC value of '0' falls into the first bin # Unused ADC bins should have a limit of 4095 and be the highest ADC bins # At least one bin limit should be 4095 (full range covered) # Slew Corrections come after the QT LUT (ie after TAC Offset/ADC Pedestal Subtraction) # Slew Corrections come before QT Channel Masks #VP001 East 0x16 4 8 0 30 60 95 135 200 300 600 4095 0x16 4 8 1 120 66 33 13 -4 -20 -39 -67 0x16 5 8 0 30 60 95 135 200 300 600 4095 0x16 5 8 1 112 62 28 8 -8 -24 -43 -70 0x16 6 8 0 30 60 95 135 200 300 600 4095 0x16 6 8 1 117 66 30 10 -7 -23 -42 -70 0x16 7 8 0 30 60 95 135 200 300 600 4095 0x16 7 8 1 118 64 30 10 -6 -22 -41 -67 0x16 12 8 0 30 60 95 135 200 300 600 4095 0x16 12 8 1 149 95 55 31 12 -6 -27 -55 0x16 13 8 0 30 60 95 135 200 300 600 4095 0x16 13 8 1 140 92 56 35 17 1 -19 -45 0x16 14 8 0 30 60 95 135 200 300 600 4095 0x16 14 8 1 140 88 51 29 10 -7 -28 -57 0x16 15 8 0 30 60 95 135 200 300 600 4095 0x16 15 8 1 134 84 48 26 8 -9 -28 -55 0x16 20 8 0 30 60 95 135 200 300 600 4095 0x16 20 8 1 122 70 33 13 -2 -18 -36 -63 0x16 21 8 0 30 60 95 135 200 300 600 4095 0x16 21 8 1 122 72 35 15 -1 -16 -34 -62 0x16 22 8 0 30 60 95 135 200 300 600 4095 0x16 22 8 1 124 73 35 14 -3 -19 -37 -65 0x16 23 8 0 30 60 95 135 200 300 600 4095 0x16 23 8 1 131 77 43 23 6 -10 -30 -57 0x16 28 8 0 30 60 95 135 200 300 600 4095 0x16 28 8 1 112 59 24 5 -11 -26 -44 -69 0x16 29 8 0 30 60 95 135 200 300 600 4095 0x16 29 8 1 119 64 29 9 -7 -23 -41 -66 0x16 30 8 0 30 60 95 135 200 300 600 4095 0x16 30 8 1 -21 -22 -23 -25 -27 -31 -36 -48 0x16 31 8 0 30 60 95 135 200 300 600 4095 0x16 31 8 1 115 60 27 8 -8 -24 -42 -69 #VP002 West 0x18 4 8 0 30 60 95 135 200 300 600 4095 0x18 4 8 1 106 52 19 -2 -19 -31 -49 -81 0x18 5 8 0 30 60 95 135 200 300 600 4095 0x18 5 8 1 92 38 9 -12 -28 -41 -57 -88 0x18 6 8 0 30 60 95 135 200 300 600 4095 0x18 6 8 1 93 43 10 -10 -27 -42 -59 -89 0x18 7 8 0 30 60 95 135 200 300 600 4095 0x18 7 8 1 122 63 26 1 -15 -31 -51 -83 0x18 12 8 0 30 60 95 135 200 300 600 4095 0x18 12 8 1 93 37 3 -16 -31 -45 -63 -89 0x18 13 8 0 30 60 95 135 200 300 600 4095 0x18 13 8 1 95 42 7 -13 -28 -43 -61 -95 0x18 14 8 0 30 60 95 135 200 300 600 4095 0x18 14 8 1 101 51 12 -10 -27 -44 -63 -97 0x18 15 8 0 30 60 95 135 200 300 600 4095 0x18 15 8 1 92 38 4 -17 -33 -47 -65 -96 0x18 20 8 0 30 60 95 135 200 300 600 4095 0x18 20 8 1 79 25 -7 -26 -46 -59 -77 -106 0x18 21 8 0 30 60 95 135 200 300 600 4095 0x18 21 8 1 79 27 -4 -22 -39 -51 -68 -93 0x18 22 8 0 30 60 95 135 200 300 600 4095 0x18 22 8 1 86 34 3 -18 -34 -48 -65 -91 0x18 23 8 0 30 60 95 135 200 300 600 4095 0x18 23 8 1 106 50 14 -9 -25 -40 -58 -90 0x18 28 8 0 30 60 95 135 200 300 600 4095 0x18 28 8 1 69 24 -3 -18 -28 -39 -53 -76 0x18 29 8 0 30 60 95 135 200 300 600 4095 0x18 29 8 1 70 16 -11 -31 -48 -59 -77 -103 0x18 30 8 0 30 60 95 135 200 300 600 4095 0x18 30 8 1 76 25 -7 -28 -44 -58 -75 -102 0x18 31 8 0 30 60 95 135 200 300 600 4095 0x18 31 8 1 78 24 -10 -30 -48 -62 -80 -109