# Board Channel NumBins BinOrOffset ADCBinLimit0 ADCBinLimit1 ... # Board Channel NumBins BinOrOffset TACOffsetBin0 TACOffsetBin1 ... # Board is 0xYY where YY is top two hex digits of board address # Channel is 0-31; only TAC channels are valid (4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31) # BinOrOffset = 0 for a Bin Limit row, 1 for an Offset row # NumBins must be exactly equal to the number of ADC Bins implemented in the QT VHDL # All ADC Bin Limits must be defined # Each ADC Bin Limit must be equal to or greater than the previous bin limit # An ADC value is in bin 'N' if BinLimit[N-1] < ADC <= BinLimit[N] # The first bin has an implied lower limit of '0' # An ADC value of '0' falls into the first bin # Unused ADC bins should have a limit of 4095 and be the highest ADC bins # At least one bin limit should be 4095 (full range covered) # Slew Corrections come after the QT LUT (ie after TAC Offset/ADC Pedestal Subtraction) # Slew Corrections come before QT Channel Masks #VP001 East 0x16 4 8 0 30 60 95 135 200 300 600 4095 0x16 4 8 1 126 71 38 18 1 -15 -33 -60 0x16 5 8 0 30 60 95 135 200 300 600 4095 0x16 5 8 1 113 63 31 12 -3 -18 -36 -62 0x16 6 8 0 30 60 95 135 200 300 600 4095 0x16 6 8 1 127 76 40 20 3 -13 -32 -60 0x16 7 8 0 30 60 95 135 200 300 600 4095 0x16 7 8 1 118 68 34 16 0 -15 -34 -59 0x16 12 8 0 30 60 95 135 200 300 600 4095 0x16 12 8 1 126 73 37 16 -1 -18 -37 -62 0x16 13 8 0 30 60 95 135 200 300 600 4095 0x16 13 8 1 115 68 37 18 2 -13 -31 -55 0x16 14 8 0 30 60 95 135 200 300 600 4095 0x16 14 8 1 122 72 37 17 0 -17 -36 -64 0x16 15 8 0 30 60 95 135 200 300 600 4095 0x16 15 8 1 113 64 32 13 -3 -18 -36 -61 0x16 20 8 0 30 60 95 135 200 300 600 4095 0x16 20 8 1 114 63 27 9 -7 -21 -38 -64 0x16 21 8 0 30 60 95 135 200 300 600 4095 0x16 21 8 1 107 59 26 8 -6 -20 -37 -62 0x16 22 8 0 30 60 95 135 200 300 600 4095 0x16 22 8 1 106 57 23 4 -11 -26 -43 -69 0x16 23 8 0 30 60 95 135 200 300 600 4095 0x16 23 8 1 123 69 37 17 1 -15 -34 -60 0x16 28 8 0 30 60 95 135 200 300 600 4095 0x16 28 8 1 124 72 35 16 0 -15 -33 -59 0x16 29 8 0 30 60 95 135 200 300 600 4095 0x16 29 8 1 131 78 40 20 3 -13 -31 -57 0x16 30 8 0 30 60 95 135 200 300 600 4095 0x16 30 8 1 -6 -7 -9 -9 -12 -14 -20 -32 0x16 31 8 0 30 60 95 135 200 300 600 4095 0x16 31 8 1 121 69 34 15 -1 -17 -35 -63 #VP002 West 0x18 4 8 0 30 60 95 135 200 300 600 4095 0x18 4 8 1 95 39 9 -11 -27 -39 -56 -84 0x18 5 8 0 30 60 95 135 200 300 600 4095 0x18 5 8 1 82 31 1 -19 -33 -46 -61 -90 0x18 6 8 0 30 60 95 135 200 300 600 4095 0x18 6 8 1 96 42 10 -11 -26 -41 -58 -89 0x18 7 8 0 30 60 95 135 200 300 600 4095 0x18 7 8 1 95 39 4 -18 -34 -48 -67 -97 0x18 12 8 0 30 60 95 135 200 300 600 4095 0x18 12 8 1 121 63 27 5 -10 -27 -46 -75 0x18 13 8 0 30 60 95 135 200 300 600 4095 0x18 13 8 1 109 55 20 -1 -16 -32 -50 -85 0x18 14 8 0 30 60 95 135 200 300 600 4095 0x18 14 8 1 111 55 20 -2 -19 -34 -53 -86 0x18 15 8 0 30 60 95 135 200 300 600 4095 0x18 15 8 1 116 60 24 3 -15 -31 -50 -82 0x18 20 8 0 30 60 95 135 200 300 600 4095 0x18 20 8 1 94 46 12 -8 -26 -40 -58 -87 0x18 21 8 0 30 60 95 135 200 300 600 4095 0x18 21 8 1 88 37 6 -13 -29 -42 -59 -85 0x18 22 8 0 30 60 95 135 200 300 600 4095 0x18 22 8 1 103 55 23 2 -15 -29 -47 -73 0x18 23 8 0 30 60 95 135 200 300 600 4095 0x18 23 8 1 117 64 30 9 -6 -21 -38 -69 0x18 28 8 0 30 60 95 135 200 300 600 4095 0x18 28 8 1 92 41 12 -5 -19 -31 -46 -70 0x18 29 8 0 30 60 95 135 200 300 600 4095 0x18 29 8 1 95 41 9 -11 -29 -43 -60 -86 0x18 30 8 0 30 60 95 135 200 300 600 4095 0x18 30 8 1 98 46 11 -11 -29 -43 -62 -90 0x18 31 8 0 30 60 95 135 200 300 600 4095 0x18 31 8 1 94 39 5 -16 -33 -47 -64 -92