# Board Channel NumBins BinOrOffset ADCBinLimit0 ADCBinLimit1 ... # Board Channel NumBins BinOrOffset TACOffsetBin0 TACOffsetBin1 ... # Board is 0xYY where YY is top two hex digits of board address # Channel is 0-31; only TAC channels are valid (4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31) # BinOrOffset = 0 for a Bin Limit row, 1 for an Offset row # NumBins must be exactly equal to the number of ADC Bins implemented in the QT VHDL # All ADC Bin Limits must be defined # Each ADC Bin Limit must be equal to or greater than the previous bin limit # An ADC value is in bin 'N' if BinLimit[N-1] < ADC <= BinLimit[N] # The first bin has an implied lower limit of '0' # An ADC value of '0' falls into the first bin # Unused ADC bins should have a limit of 4095 and be the highest ADC bins # At least one bin limit should be 4095 (full range covered) # Slew Corrections come after the QT LUT (ie after TAC Offset/ADC Pedestal Subtraction) # Slew Corrections come before QT Channel Masks #VP001 East 0x16 4 8 0 30 60 95 135 200 300 600 4095 0x16 4 8 1 131 78 45 26 10 -6 -24 -48 0x16 5 8 0 30 60 95 135 200 300 600 4095 0x16 5 8 1 118 70 39 20 5 -9 -26 -50 0x16 6 8 0 30 60 95 135 200 300 600 4095 0x16 6 8 1 132 83 47 28 11 -4 -22 -48 0x16 7 8 0 30 60 95 135 200 300 600 4095 0x16 7 8 1 122 75 42 24 8 -6 -24 -47 0x16 12 8 0 30 60 95 135 200 300 600 4095 0x16 12 8 1 130 78 43 23 6 -10 -28 -51 0x16 13 8 0 30 60 95 135 200 300 600 4095 0x16 13 8 1 118 72 42 24 9 -6 -23 -44 0x16 14 8 0 30 60 95 135 200 300 600 4095 0x16 14 8 1 124 76 43 23 7 -9 -28 -53 0x16 15 8 0 30 60 95 135 200 300 600 4095 0x16 15 8 1 115 69 38 20 4 -11 -28 -50 0x16 20 8 0 30 60 95 135 200 300 600 4095 0x16 20 8 1 120 71 36 18 3 -11 -27 -51 0x16 21 8 0 30 60 95 135 200 300 600 4095 0x16 21 8 1 114 67 35 18 4 -10 -25 -48 0x16 22 8 0 30 60 95 135 200 300 600 4095 0x16 22 8 1 113 66 33 14 -1 -15 -32 -55 0x16 23 8 0 30 60 95 135 200 300 600 4095 0x16 23 8 1 129 77 46 26 10 -5 -23 -47 0x16 28 8 0 30 60 95 135 200 300 600 4095 0x16 28 8 1 128 78 43 24 8 -6 -24 -47 0x16 29 8 0 30 60 95 135 200 300 600 4095 0x16 29 8 1 136 84 47 27 11 -4 -22 -45 0x16 30 8 0 30 60 95 135 200 300 600 4095 0x16 30 8 1 4 2 2 0 -1 -5 -9 -22 0x16 31 8 0 30 60 95 135 200 300 600 4095 0x16 31 8 1 126 76 42 23 7 -8 -26 -51 #VP002 West 0x18 4 8 0 30 60 95 135 200 300 600 4095 0x18 4 8 1 108 52 23 4 -12 -24 -41 -68 0x18 5 8 0 30 60 95 135 200 300 600 4095 0x18 5 8 1 96 44 15 -5 -20 -32 -46 -74 0x18 6 8 0 30 60 95 135 200 300 600 4095 0x18 6 8 1 110 55 23 2 -12 -26 -43 -73 0x18 7 8 0 30 60 95 135 200 300 600 4095 0x18 7 8 1 103 52 18 -3 -20 -32 -51 -80 0x18 12 8 0 30 60 95 135 200 300 600 4095 0x18 12 8 1 130 77 40 18 4 -12 -30 -59 0x18 13 8 0 30 60 95 135 200 300 600 4095 0x18 13 8 1 118 67 34 12 -1 -17 -35 -70 0x18 14 8 0 30 60 95 135 200 300 600 4095 0x18 14 8 1 123 67 34 12 -4 -21 -39 -70 0x18 15 8 0 30 60 95 135 200 300 600 4095 0x18 15 8 1 126 72 38 15 -1 -16 -37 -67 0x18 20 8 0 30 60 95 135 200 300 600 4095 0x18 20 8 1 105 59 26 6 -14 -26 -43 -71 0x18 21 8 0 30 60 95 135 200 300 600 4095 0x18 21 8 1 97 49 18 0 -16 -27 -46 -70 0x18 22 8 0 30 60 95 135 200 300 600 4095 0x18 22 8 1 117 67 34 15 -1 -14 -34 -60 0x18 23 8 0 30 60 95 135 200 300 600 4095 0x18 23 8 1 129 74 44 22 7 -9 -25 -55 0x18 28 8 0 30 60 95 135 200 300 600 4095 0x18 28 8 1 103 53 26 8 -5 -17 -32 -55 0x18 29 8 0 30 60 95 135 200 300 600 4095 0x18 29 8 1 107 53 22 2 -15 -29 -45 -70 0x18 30 8 0 30 60 95 135 200 300 600 4095 0x18 30 8 1 109 58 25 2 -14 -28 -47 -75 0x18 31 8 0 30 60 95 135 200 300 600 4095 0x18 31 8 1 110 51 19 -4 -19 -32 -49 -74