# Board Channel NumBins BinOrOffset ADCBinLimit0 ADCBinLimit1 ... # Board Channel NumBins BinOrOffset TACOffsetBin0 TACOffsetBin1 ... # Board is 0xYY where YY is top two hex digits of board address # Channel is 0-31; only TAC channels are valid (4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31) # BinOrOffset = 0 for a Bin Limit row, 1 for an Offset row # NumBins must be exactly equal to the number of ADC Bins implemented in the QT VHDL # All ADC Bin Limits must be defined # Each ADC Bin Limit must be equal to or greater than the previous bin limit # An ADC value is in bin 'N' if BinLimit[N-1] < ADC <= BinLimit[N] # The first bin has an implied lower limit of '0' # An ADC value of '0' falls into the first bin # Unused ADC bins should have a limit of 4095 and be the highest ADC bins # At least one bin limit should be 4095 (full range covered) # Slew Corrections come after the QT LUT (ie after TAC Offset/ADC Pedestal Subtraction) # Slew Corrections come before QT Channel Masks #VP001 East 0x16 4 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 4 8 1 0 0 0 0 0 0 0 0 0x16 5 8 0 30 60 95 135 200 300 600 4095 0x16 5 8 1 104 56 26 7 -8 -22 -39 -59 0x16 6 8 0 30 60 95 135 200 300 600 4095 0x16 6 8 1 116 66 33 13 -3 -18 -38 -60 0x16 7 8 0 30 60 95 135 200 300 600 4095 0x16 7 8 1 108 59 27 8 -7 -22 -39 -59 0x16 12 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 12 8 1 0 0 0 0 0 0 0 0 0x16 13 8 0 30 60 95 135 200 300 600 4095 0x16 13 8 1 100 48 19 1 -14 -29 -46 -66 0x16 14 8 0 30 60 95 135 200 300 600 4095 0x16 14 8 1 115 58 27 7 -9 -25 -44 -67 0x16 15 8 0 30 60 95 135 200 300 600 4095 0x16 15 8 1 105 53 23 5 -10 -25 -41 -61 0x16 20 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 20 8 1 0 0 0 0 0 0 0 0 0x16 21 8 0 30 60 95 135 200 300 600 4095 0x16 21 8 1 96 47 19 2 -13 -25 -40 -60 0x16 22 8 0 30 60 95 135 200 300 600 4095 0x16 22 8 1 101 51 21 3 -13 -27 -43 -64 0x16 23 8 0 30 60 95 135 200 300 600 4095 0x16 23 8 1 110 55 24 5 -10 -26 -43 -62 0x16 28 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 28 8 1 0 0 0 0 0 0 0 0 0x16 29 8 0 30 60 95 135 200 300 600 4095 0x16 29 8 1 121 71 38 19 3 -12 -30 -50 0x16 30 8 0 30 60 95 135 200 300 600 4095 0x16 30 8 1 113 67 37 18 3 -12 -29 -50 0x16 31 8 0 30 60 95 135 200 300 600 4095 0x16 31 8 1 114 67 37 19 4 -11 -29 -52 #VP002 West 0x18 4 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 4 8 1 0 0 0 0 0 0 0 0 0x18 5 8 0 30 60 95 135 200 300 600 4095 0x18 5 8 1 0 0 0 0 0 0 0 0 0x18 6 8 0 30 60 95 135 200 300 600 4095 0x18 6 8 1 78 23 -8 -27 -43 -58 -76 -97 0x18 7 8 0 30 60 95 135 200 300 600 4095 0x18 7 8 1 75 20 -13 -32 -47 -62 -80 -101 0x18 12 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 12 8 1 0 0 0 0 0 0 0 0 0x18 13 8 0 30 60 95 135 200 300 600 4095 0x18 13 8 1 89 39 8 -11 -26 -42 -60 -84 0x18 14 8 0 30 60 95 135 200 300 600 4095 0x18 14 8 1 95 38 7 -12 -28 -43 -60 -82 0x18 15 8 0 30 60 95 135 200 300 600 4095 0x18 15 8 1 105 48 15 -5 -21 -37 -56 -79 0x18 20 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 20 8 1 0 0 0 0 0 0 0 0 0x18 21 8 0 30 60 95 135 200 300 600 4095 0x18 21 8 1 83 35 6 -11 -26 -39 -56 -75 0x18 22 8 0 30 60 95 135 200 300 600 4095 0x18 22 8 1 83 36 7 -10 -25 -39 -56 -76 0x18 23 8 0 30 60 95 135 200 300 600 4095 0x18 23 8 1 89 37 8 -11 -26 -40 -56 -77 0x18 28 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 28 8 1 0 0 0 0 0 0 0 0 0x18 29 8 0 30 60 95 135 200 300 600 4095 0x18 29 8 1 81 32 4 -13 -28 -41 -57 -77 0x18 30 8 0 30 60 95 135 200 300 600 4095 0x18 30 8 1 86 36 7 -12 -26 -40 -57 -78 0x18 31 8 0 30 60 95 135 200 300 600 4095 0x18 31 8 1 84 34 4 -14 -29 -43 -60 -81