# Board Channel NumBins BinOrOffset ADCBinLimit0 ADCBinLimit1 ... # Board Channel NumBins BinOrOffset TACOffsetBin0 TACOffsetBin1 ... # Board is 0xYY where YY is top two hex digits of board address # Channel is 0-31; only TAC channels are valid (4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31) # BinOrOffset = 0 for a Bin Limit row, 1 for an Offset row # NumBins must be exactly equal to the number of ADC Bins implemented in the QT VHDL # All ADC Bin Limits must be defined # Each ADC Bin Limit must be equal to or greater than the previous bin limit # An ADC value is in bin 'N' if BinLimit[N-1] < ADC <= BinLimit[N] # The first bin has an implied lower limit of '0' # An ADC value of '0' falls into the first bin # Unused ADC bins should have a limit of 4095 and be the highest ADC bins # At least one bin limit should be 4095 (full range covered) # Slew Corrections come after the QT LUT (ie after TAC Offset/ADC Pedestal Subtraction) # Slew Corrections come before QT Channel Masks #VP001 East 0x16 4 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 4 8 1 0 0 0 0 0 0 0 0 0x16 5 8 0 30 60 95 135 200 300 600 4095 0x16 5 8 1 105 53 22 4 -10 -23 -40 -58 0x16 6 8 0 30 60 95 135 200 300 600 4095 0x16 6 8 1 109 61 33 15 0 -13 -28 -47 0x16 7 8 0 30 60 95 135 200 300 600 4095 0x16 7 8 1 107 51 24 6 -8 -21 -38 -56 0x16 12 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 12 8 1 0 0 0 0 0 0 0 0 0x16 13 8 0 30 60 95 135 200 300 600 4095 0x16 13 8 1 108 54 23 5 -11 -25 -43 -62 0x16 14 8 0 30 60 95 135 200 300 600 4095 0x16 14 8 1 123 66 33 15 -1 -17 -33 -54 0x16 15 8 0 30 60 95 135 200 300 600 4095 0x16 15 8 1 107 53 22 5 -10 -25 -40 -58 0x16 20 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 20 8 1 0 0 0 0 0 0 0 0 0x16 21 8 0 30 60 95 135 200 300 600 4095 0x16 21 8 1 101 49 21 3 -11 -24 -38 -56 0x16 22 8 0 30 60 95 135 200 300 600 4095 0x16 22 8 1 83 37 13 -4 -15 -27 -41 -60 0x16 23 8 0 30 60 95 135 200 300 600 4095 0x16 23 8 1 106 53 23 5 -10 -24 -40 -58 0x16 28 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 28 8 1 0 0 0 0 0 0 0 0 0x16 29 8 0 30 60 95 135 200 300 600 4095 0x16 29 8 1 99 45 16 -1 -15 -29 -45 -63 0x16 30 8 0 30 60 95 135 200 300 600 4095 0x16 30 8 1 92 45 17 0 -13 -26 -40 -59 0x16 31 8 0 30 60 95 135 200 300 600 4095 0x16 31 8 1 109 51 22 4 -10 -23 -39 -59 #VP002 West 0x18 4 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 4 8 1 0 0 0 0 0 0 0 0 0x18 5 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 5 8 1 0 0 0 0 0 0 0 0 0x18 6 8 0 30 60 95 135 200 300 600 4095 0x18 6 8 1 75 22 -7 -28 -42 -56 -70 -93 0x18 7 8 0 30 60 95 135 200 300 600 4095 0x18 7 8 1 119 56 23 2 -17 -32 -50 -73 0x18 12 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 12 8 1 0 0 0 0 0 0 0 0 0x18 13 8 0 30 60 95 135 200 300 600 4095 0x18 13 8 1 126 69 42 25 9 -4 -21 -48 0x18 14 8 0 30 60 95 135 200 300 600 4095 0x18 14 8 1 101 48 20 -1 -14 -30 -45 -63 0x18 15 8 0 30 60 95 135 200 300 600 4095 0x18 15 8 1 96 43 14 -5 -20 -33 -49 -67 0x18 20 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 20 8 1 0 0 0 0 0 0 0 0 0x18 21 8 0 30 60 95 135 200 300 600 4095 0x18 21 8 1 85 40 16 1 -11 -23 -37 -54 0x18 22 8 0 30 60 95 135 200 300 600 4095 0x18 22 8 1 86 37 12 -4 -19 -32 -48 -67 0x18 23 8 0 30 60 95 135 200 300 600 4095 0x18 23 8 1 106 49 17 -2 -19 -33 -52 -73 0x18 28 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 28 8 1 0 0 0 0 0 0 0 0 0x18 29 8 0 30 60 95 135 200 300 600 4095 0x18 29 8 1 89 40 14 -2 -15 -28 -43 -61 0x18 30 8 0 30 60 95 135 200 300 600 4095 0x18 30 8 1 85 37 14 -2 -16 -29 -44 -63 0x18 31 8 0 30 60 95 135 200 300 600 4095 0x18 31 8 1 104 48 19 1 -15 -29 -46 -67