# Board Channel NumBins BinOrOffset ADCBinLimit0 ADCBinLimit1 ... # Board Channel NumBins BinOrOffset TACOffsetBin0 TACOffsetBin1 ... # Board is 0xYY where YY is top two hex digits of board address # Channel is 0-31; only TAC channels are valid (4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31) # BinOrOffset = 0 for a Bin Limit row, 1 for an Offset row # NumBins must be exactly equal to the number of ADC Bins implemented in the QT VHDL # All ADC Bin Limits must be defined # Each ADC Bin Limit must be equal to or greater than the previous bin limit # An ADC value is in bin 'N' if BinLimit[N-1] < ADC <= BinLimit[N] # The first bin has an implied lower limit of '0' # An ADC value of '0' falls into the first bin # Unused ADC bins should have a limit of 4095 and be the highest ADC bins # At least one bin limit should be 4095 (full range covered) # Slew Corrections come after the QT LUT (ie after TAC Offset/ADC Pedestal Subtraction) # Slew Corrections come before QT Channel Masks #VP001 East 0x16 4 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 4 8 1 0 0 0 0 0 0 0 0 0x16 5 8 0 30 60 95 135 200 300 600 4095 0x16 5 8 1 112 64 37 18 4 -9 -26 -50 0x16 6 8 0 30 60 95 135 200 300 600 4095 0x16 6 8 1 115 63 36 18 4 -10 -27 -51 0x16 7 8 0 30 60 95 135 200 300 600 4095 0x16 7 8 1 123 73 40 20 5 -11 -28 -54 0x16 12 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 12 8 1 0 0 0 0 0 0 0 0 0x16 13 8 0 30 60 95 135 200 300 600 4095 0x16 13 8 1 140 86 51 31 14 -2 -21 -47 0x16 14 8 0 30 60 95 135 200 300 600 4095 0x16 14 8 1 136 83 48 27 10 -6 -25 -52 0x16 15 8 0 30 60 95 135 200 300 600 4095 0x16 15 8 1 136 85 52 31 15 0 -18 -44 0x16 20 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 20 8 1 0 0 0 0 0 0 0 0 0x16 21 8 0 30 60 95 135 200 300 600 4095 0x16 21 8 1 124 73 40 21 6 -8 -25 -51 0x16 22 8 0 30 60 95 135 200 300 600 4095 0x16 22 8 1 102 51 23 7 -6 -18 -32 -55 0x16 23 8 0 30 60 95 135 200 300 600 4095 0x16 23 8 1 127 74 42 23 7 -9 -26 -52 0x16 28 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 28 8 1 0 0 0 0 0 0 0 0 0x16 29 8 0 30 60 95 135 200 300 600 4095 0x16 29 8 1 112 56 22 4 -12 -27 -44 -69 0x16 30 8 0 30 60 95 135 200 300 600 4095 0x16 30 8 1 103 54 23 5 -10 -24 -40 -65 0x16 31 8 0 30 60 95 135 200 300 600 4095 0x16 31 8 1 107 51 19 1 -14 -29 -45 -72 #VP002 West 0x18 4 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 4 8 1 0 0 0 0 0 0 0 0 0x18 5 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 5 8 1 0 0 0 0 0 0 0 0 0x18 6 8 0 30 60 95 135 200 300 600 4095 0x18 6 8 1 125 71 45 23 5 -3 -23 -54 0x18 7 8 0 30 60 95 135 200 300 600 4095 0x18 7 8 1 135 71 36 11 -4 -19 -39 -72 0x18 12 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 12 8 1 0 0 0 0 0 0 0 0 0x18 13 8 0 30 60 95 135 200 300 600 4095 0x18 13 8 1 116 58 26 8 -4 -19 -37 -70 0x18 14 8 0 30 60 95 135 200 300 600 4095 0x18 14 8 1 119 67 30 11 -4 -23 -38 -67 0x18 15 8 0 30 60 95 135 200 300 600 4095 0x18 15 8 1 117 57 26 9 -6 -19 -35 -62 0x18 20 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 20 8 1 0 0 0 0 0 0 0 0 0x18 21 8 0 30 60 95 135 200 300 600 4095 0x18 21 8 1 118 61 32 16 0 -12 -26 -48 0x18 22 8 0 30 60 95 135 200 300 600 4095 0x18 22 8 1 97 41 9 -8 -22 -33 -50 -76 0x18 23 8 0 30 60 95 135 200 300 600 4095 0x18 23 8 1 128 70 36 15 -3 -16 -33 -66 0x18 28 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 28 8 1 0 0 0 0 0 0 0 0 0x18 29 8 0 30 60 95 135 200 300 600 4095 0x18 29 8 1 116 67 39 18 8 -6 -22 -46 0x18 30 8 0 30 60 95 135 200 300 600 4095 0x18 30 8 1 126 72 44 23 8 -3 -22 -46 0x18 31 8 0 30 60 95 135 200 300 600 4095 0x18 31 8 1 135 74 45 23 10 -3 -20 -51