# Board Channel NumBins BinOrOffset ADCBinLimit0 ADCBinLimit1 ... # Board Channel NumBins BinOrOffset TACOffsetBin0 TACOffsetBin1 ... # Board is 0xYY where YY is top two hex digits of board address # Channel is 0-31; only TAC channels are valid (4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31) # BinOrOffset = 0 for a Bin Limit row, 1 for an Offset row # NumBins must be exactly equal to the number of ADC Bins implemented in the QT VHDL # All ADC Bin Limits must be defined # Each ADC Bin Limit must be equal to or greater than the previous bin limit # An ADC value is in bin 'N' if BinLimit[N-1] < ADC <= BinLimit[N] # The first bin has an implied lower limit of '0' # An ADC value of '0' falls into the first bin # Unused ADC bins should have a limit of 4095 and be the highest ADC bins # At least one bin limit should be 4095 (full range covered) # Slew Corrections come after the QT LUT (ie after TAC Offset/ADC Pedestal Subtraction) # Slew Corrections come before QT Channel Masks #VP001 East 0x16 4 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 4 8 1 0 0 0 0 0 0 0 0 0x16 5 8 0 30 60 95 135 200 300 600 4095 0x16 5 8 1 135 79 44 22 5 -11 -31 -59 0x16 6 8 0 30 60 95 135 200 300 600 4095 0x16 6 8 1 135 78 44 22 5 -11 -30 -58 0x16 7 8 0 30 60 95 135 200 300 600 4095 0x16 7 8 1 125 71 39 20 4 -11 -29 -56 0x16 12 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 12 8 1 0 0 0 0 0 0 0 0 0x16 13 8 0 30 60 95 135 200 300 600 4095 0x16 13 8 1 137 80 46 26 10 -6 -25 -51 0x16 14 8 0 30 60 95 135 200 300 600 4095 0x16 14 8 1 131 77 43 22 5 -12 -31 -59 0x16 15 8 0 30 60 95 135 200 300 600 4095 0x16 15 8 1 133 79 47 27 11 -4 -23 -49 0x16 20 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 20 8 1 0 0 0 0 0 0 0 0 0x16 21 8 0 30 60 95 135 200 300 600 4095 0x16 21 8 1 98 49 19 2 -12 -24 -40 -64 0x16 22 8 0 30 60 95 135 200 300 600 4095 0x16 22 8 1 111 54 19 1 -14 -29 -46 -72 0x16 23 8 0 30 60 95 135 200 300 600 4095 0x16 23 8 1 112 56 22 2 -14 -31 -49 -75 0x16 28 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 28 8 1 0 0 0 0 0 0 0 0 0x16 29 8 0 30 60 95 135 200 300 600 4095 0x16 29 8 1 137 75 39 17 1 -16 -35 -62 0x16 30 8 0 30 60 95 135 200 300 600 4095 0x16 30 8 1 122 67 36 17 0 -14 -32 -59 0x16 31 8 0 30 60 95 135 200 300 600 4095 0x16 31 8 1 122 64 34 14 -1 -16 -34 -63 #VP002 West 0x18 4 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 4 8 1 0 0 0 0 0 0 0 0 0x18 5 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 5 8 1 0 0 0 0 0 0 0 0 0x18 6 8 0 30 60 95 135 200 300 600 4095 0x18 6 8 1 93 35 3 -22 -34 -49 -67 -96 0x18 7 8 0 30 60 95 135 200 300 600 4095 0x18 7 8 1 89 25 -14 -34 -48 -64 -80 -111 0x18 12 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 12 8 1 0 0 0 0 0 0 0 0 0x18 13 8 0 30 60 95 135 200 300 600 4095 0x18 13 8 1 139 73 38 20 3 -11 -28 -61 0x18 14 8 0 30 60 95 135 200 300 600 4095 0x18 14 8 1 131 70 35 16 1 -15 -32 -63 0x18 15 8 0 30 60 95 135 200 300 600 4095 0x18 15 8 1 134 74 40 19 3 -12 -29 -61 0x18 20 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 20 8 1 0 0 0 0 0 0 0 0 0x18 21 8 0 30 60 95 135 200 300 600 4095 0x18 21 8 1 106 56 25 7 -8 -22 -37 -63 0x18 22 8 0 30 60 95 135 200 300 600 4095 0x18 22 8 1 89 30 1 -17 -30 -45 -60 -90 0x18 23 8 0 30 60 95 135 200 300 600 4095 0x18 23 8 1 116 57 26 5 -12 -24 -41 -74 0x18 28 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 28 8 1 0 0 0 0 0 0 0 0 0x18 29 8 0 30 60 95 135 200 300 600 4095 0x18 29 8 1 98 38 8 -12 -27 -42 -59 -86 0x18 30 8 0 30 60 95 135 200 300 600 4095 0x18 30 8 1 106 46 12 -8 -22 -38 -56 -83 0x18 31 8 0 30 60 95 135 200 300 600 4095 0x18 31 8 1 106 45 13 -10 -20 -37 -55 -83