# Board Channel NumBins BinOrOffset ADCBinLimit0 ADCBinLimit1 ... # Board Channel NumBins BinOrOffset TACOffsetBin0 TACOffsetBin1 ... # Board is 0xYY where YY is top two hex digits of board address # Channel is 0-31; only TAC channels are valid (4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31) # BinOrOffset = 0 for a Bin Limit row, 1 for an Offset row # NumBins must be exactly equal to the number of ADC Bins implemented in the QT VHDL # All ADC Bin Limits must be defined # Each ADC Bin Limit must be equal to or greater than the previous bin limit # An ADC value is in bin 'N' if BinLimit[N-1] < ADC <= BinLimit[N] # The first bin has an implied lower limit of '0' # An ADC value of '0' falls into the first bin # Unused ADC bins should have a limit of 4095 and be the highest ADC bins # At least one bin limit should be 4095 (full range covered) # Slew Corrections come after the QT LUT (ie after TAC Offset/ADC Pedestal Subtraction) # Slew Corrections come before QT Channel Masks #VP001 East 0x16 4 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 4 8 1 0 0 0 0 0 0 0 0 0x16 5 8 0 30 60 95 135 200 300 600 4095 0x16 5 8 1 106 58 28 13 -1 -14 -30 -54 0x16 6 8 0 30 60 95 135 200 300 600 4095 0x16 6 8 1 106 59 28 13 -1 -14 -29 -54 0x16 7 8 0 30 60 95 135 200 300 600 4095 0x16 7 8 1 114 65 30 12 -3 -16 -33 -58 0x16 12 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 12 8 1 0 0 0 0 0 0 0 0 0x16 13 8 0 30 60 95 135 200 300 600 4095 0x16 13 8 1 111 60 26 8 -8 -24 -41 -69 0x16 14 8 0 30 60 95 135 200 300 600 4095 0x16 14 8 1 115 61 27 8 -8 -22 -40 -67 0x16 15 8 0 30 60 95 135 200 300 600 4095 0x16 15 8 1 115 62 28 9 -6 -21 -38 -64 0x16 20 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 20 8 1 0 0 0 0 0 0 0 0 0x16 21 8 0 30 60 95 135 200 300 600 4095 0x16 21 8 1 130 82 51 30 13 0 -16 -43 0x16 22 8 0 30 60 95 135 200 300 600 4095 0x16 22 8 1 68 19 -4 -17 -28 -37 -49 -68 0x16 23 8 0 30 60 95 135 200 300 600 4095 0x16 23 8 1 117 66 31 12 -3 -17 -34 -60 0x16 28 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 28 8 1 0 0 0 0 0 0 0 0 0x16 29 8 0 30 60 95 135 200 300 600 4095 0x16 29 8 1 110 63 27 6 -8 -23 -38 -65 0x16 30 8 0 30 60 95 135 200 300 600 4095 0x16 30 8 1 96 50 18 1 -13 -26 -42 -67 0x16 31 8 0 30 60 95 135 200 300 600 4095 0x16 31 8 1 106 59 24 6 -8 -22 -37 -64 #VP002 West 0x18 4 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 4 8 1 0 0 0 0 0 0 0 0 0x18 5 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 5 8 1 0 0 0 0 0 0 0 0 0x18 6 8 0 30 60 95 135 200 300 600 4095 0x18 6 8 1 134 83 52 34 18 2 -14 -42 0x18 7 8 0 30 60 95 135 200 300 600 4095 0x18 7 8 1 150 84 55 33 12 -7 -23 -56 0x18 12 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 12 8 1 0 0 0 0 0 0 0 0 0x18 13 8 0 30 60 95 135 200 300 600 4095 0x18 13 8 1 130 74 43 26 12 -3 -19 -50 0x18 14 8 0 30 60 95 135 200 300 600 4095 0x18 14 8 1 142 85 54 34 17 3 -16 -44 0x18 15 8 0 30 60 95 135 200 300 600 4095 0x18 15 8 1 137 78 47 31 16 -1 -14 -42 0x18 20 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 20 8 1 0 0 0 0 0 0 0 0 0x18 21 8 0 30 60 95 135 200 300 600 4095 0x18 21 8 1 132 75 47 34 15 4 -13 -36 0x18 22 8 0 30 60 95 135 200 300 600 4095 0x18 22 8 1 103 51 22 6 -9 -21 -37 -64 0x18 23 8 0 30 60 95 135 200 300 600 4095 0x18 23 8 1 135 85 51 30 11 -1 -18 -48 0x18 28 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 28 8 1 0 0 0 0 0 0 0 0 0x18 29 8 0 30 60 95 135 200 300 600 4095 0x18 29 8 1 118 65 35 19 4 -8 -22 -45 0x18 30 8 0 30 60 95 135 200 300 600 4095 0x18 30 8 1 134 81 52 34 19 6 -11 -37 0x18 31 8 0 30 60 95 135 200 300 600 4095 0x18 31 8 1 137 76 48 29 9 1 -19 -48