# Board Channel NumBins BinOrOffset ADCBinLimit0 ADCBinLimit1 ... # Board Channel NumBins BinOrOffset TACOffsetBin0 TACOffsetBin1 ... # Board is 0xYY where YY is top two hex digits of board address # Channel is 0-31; only TAC channels are valid (4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31) # BinOrOffset = 0 for a Bin Limit row, 1 for an Offset row # NumBins must be exactly equal to the number of ADC Bins implemented in the QT VHDL # All ADC Bin Limits must be defined # Each ADC Bin Limit must be equal to or greater than the previous bin limit # An ADC value is in bin 'N' if BinLimit[N-1] < ADC <= BinLimit[N] # The first bin has an implied lower limit of '0' # An ADC value of '0' falls into the first bin # Unused ADC bins should have a limit of 4095 and be the highest ADC bins # At least one bin limit should be 4095 (full range covered) # Slew Corrections come after the QT LUT (ie after TAC Offset/ADC Pedestal Subtraction) # Slew Corrections come before QT Channel Masks #VP001 East 0x16 4 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 4 8 1 0 0 0 0 0 0 0 0 0x16 5 8 0 30 60 95 135 200 300 600 4095 0x16 5 8 1 121 67 29 9 -7 -22 -40 -68 0x16 6 8 0 30 60 95 135 200 300 600 4095 0x16 6 8 1 117 66 28 8 -8 -23 -41 -70 0x16 7 8 0 30 60 95 135 200 300 600 4095 0x16 7 8 1 112 60 24 7 -8 -23 -40 -67 0x16 12 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 12 8 1 0 0 0 0 0 0 0 0 0x16 13 8 0 30 60 95 135 200 300 600 4095 0x16 13 8 1 116 57 25 6 -10 -25 -43 -70 0x16 14 8 0 30 60 95 135 200 300 600 4095 0x16 14 8 1 117 58 26 6 -10 -26 -43 -70 0x16 15 8 0 30 60 95 135 200 300 600 4095 0x16 15 8 1 115 60 28 9 -6 -21 -39 -66 0x16 20 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 20 8 1 0 0 0 0 0 0 0 0 0x16 21 8 0 30 60 95 135 200 300 600 4095 0x16 21 8 1 116 72 42 23 10 -2 -17 -42 0x16 22 8 0 30 60 95 135 200 300 600 4095 0x16 22 8 1 101 47 12 -5 -19 -33 -49 -74 0x16 23 8 0 30 60 95 135 200 300 600 4095 0x16 23 8 1 112 56 23 3 -12 -27 -44 -70 0x16 28 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x16 28 8 1 0 0 0 0 0 0 0 0 0x16 29 8 0 30 60 95 135 200 300 600 4095 0x16 29 8 1 109 58 17 -4 -19 -35 -51 -79 0x16 30 8 0 30 60 95 135 200 300 600 4095 0x16 30 8 1 91 39 6 -12 -27 -41 -57 -85 0x16 31 8 0 30 60 95 135 200 300 600 4095 0x16 31 8 1 99 51 14 -4 -19 -35 -51 -78 #VP002 West 0x18 4 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 4 8 1 0 0 0 0 0 0 0 0 0x18 5 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 5 8 1 0 0 0 0 0 0 0 0 0x18 6 8 0 30 60 95 135 200 300 600 4095 0x18 6 8 1 147 89 59 40 22 7 -8 -38 0x18 7 8 0 30 60 95 135 200 300 600 4095 0x18 7 8 1 147 87 57 33 17 3 -15 -49 0x18 12 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 12 8 1 0 0 0 0 0 0 0 0 0x18 13 8 0 30 60 95 135 200 300 600 4095 0x18 13 8 1 146 86 53 34 19 3 -13 -48 0x18 14 8 0 30 60 95 135 200 300 600 4095 0x18 14 8 1 152 92 62 42 26 12 -8 -37 0x18 15 8 0 30 60 95 135 200 300 600 4095 0x18 15 8 1 173 106 72 55 38 19 5 -27 0x18 20 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 20 8 1 0 0 0 0 0 0 0 0 0x18 21 8 0 30 60 95 135 200 300 600 4095 0x18 21 8 1 149 89 64 41 26 15 -2 -27 0x18 22 8 0 30 60 95 135 200 300 600 4095 0x18 22 8 1 123 64 31 17 0 -13 -26 -65 0x18 23 8 0 30 60 95 135 200 300 600 4095 0x18 23 8 1 152 96 61 41 25 14 -7 -37 0x18 28 8 0 4095 4095 4095 4095 4095 4095 4095 4095 0x18 28 8 1 0 0 0 0 0 0 0 0 0x18 29 8 0 30 60 95 135 200 300 600 4095 0x18 29 8 1 140 80 44 24 9 -4 -20 -45 0x18 30 8 0 30 60 95 135 200 300 600 4095 0x18 30 8 1 149 91 57 34 20 4 -13 -42 0x18 31 8 0 30 60 95 135 200 300 600 4095 0x18 31 8 1 157 95 61 42 25 13 -5 -35